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low-cost, 3.3v zero delay buffer mpc962305 idt? / ics? 3.3v zero delay buffer 1 mpc962305 rev 7 july 16, 2007 the mpc962309 is a zero delay buffer designed to distribute high-speed clocks. available in a 16-pin soic or tssop package, the device accepts one reference input and drives nine low-skew clocks. the mpc962305 is the 8-pin version of the mpc962309 which drives five outputs with one reference input. the -1h versions of these devices have hi gher drive than the -1 devices and can operate up to 100/-133 mhz frequencies. these parts have on-chip plls which lock to an input clock presented on the ref pin. the pll feedback is on-chip and is obtained from the clockout pad. features ? 1:5 lvcmos zero-delay buffer (mpc962305) ? 1:9 lvcmos zero-delay buffer (mpc962309) ? zero input-output propagation delay ? multiple low-skew outputs ? 250 ps max output-output skew ? 700 ps max device-device skew ? supports a clock i/o frequency range of 10 mhz to 133 mhz, compatible with cpu and pci bus frequencies ? low jitter, 200 ps max cycle-cycl e, and compatible with pentium ? based systems ? test mode to bypass pll (mpc962309 only. see ta b l e 3 ) ? 8-pin soic or 8-pin tssop package (mpc962305);16-pin soic or 16-pin tssop package (mpc962309) ? single 3.3 v supply ? ambient temperature range: ?40 c to +85 c ? compatible with the cy2305, cy23s05, cy2309, cy23s09 ? spread spectrum compatible ? pb-free packages available functional description the mpc962309 has two banks of four outputs each, which can be controlled by the select inputs as shown in ta b l e 3 . bank b can be tri-stated if all of the outputs are not required. select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. the mpc962305 and mpc962309 plls enters a power down state when there are no rising edges on the ref input. during this state, all of the outputs are in tristate, the pll is tur ned off, and there is less than 25.0 a of current draw for the device. the pll shuts down in one additional case as shown in ta b l e 3 . multiple mpc962305 and mpc962309 devices can accept the same input clock and distribute it throughout the system. in this situati on, the difference between the out put skews of two devices will b e less than 700 ps. all outputs have less than 200 ps of cycle-cycle jitter. the inpu t-to-output propagati on delay on both devi ces is guaranteed to be less than 350 ps and the output-to-output skew is guaran teed to be less than 250 ps. the mpc962305 and mpc962309 are available in two/three diff erent configurations, as shown on the ordering information page. the mpc962305-1/mpc962309-1 are the base parts. high drive versions of those devices, mpc962305-1h and mpc962309-1h, are available to provide faster rise and fall times of the base device. pentium ii is a trademark of intel corporation. mpc962305 mpc962309 d suffix 16-lead soic package case 751b-05 d suffix 8-lead soic package case 751-06 dt suffix 8-lead tssop package case 948j-01 ef suffix 8-lead soic package pb-free package case 751-06 ej suffix 8-lead tssop package pb-free package case 948j-01 ef suffix 16-lead soic package pb-free package case 751b-05 dt suffix 16-lead tssop package case 948f-01 ej suffix 16-lead tssop package pb-free package case 948f-01
mpc962305 low-cost, 3.3v zero delay buffer idt? / ics? 3.3v zero delay buffer 2 mpc962305 rev 7 july 16, 2007 table 1. pin description for mpc962309 pin signal description 1ref (1) 1. weak pull-down. input reference frequency, 5 v-tolerant input 2 clka1 (2) 2. weak pull-down on all outputs. buffered clock output, bank a 3 clka2 (2) buffered clock output, bank a 4v dd 3.3 v supply 5 gnd ground 6 clkb1 (2) buffered clock output, bank b 7 clkb2 (2) buffered clock output, bank b 8s2 (3) 3. weak pull-ups on these inputs. select input, bit 2 9s1 (3) select input, bit 1 10 clkb3 (2) buffered clock output, bank b 11 clkb4 (2) buffered clock output, bank b 12 gnd ground 13 v dd 3.3 v supply 14 clka3 (2) buffered clock output, bank a 15 clka4 (2) buffered clock output, bank a 16 clkout (2) buffered output, internal feedback on this pin table 2. pin description for mpc962305 pin signal description 1 ref (1) 1. weak pull-down. input reference frequency, 5 v-tolerant input 2 clk2 (2) 2. weak pull-down on all outputs. buffered clock output 3 clk1 (2) buffered clock output 4 gnd ground 5 clk3 (2) buffered clock output 6 v dd 3.3 v supply 7 clk4 (2) buffered clock output 8 clkout (2) buffered clock output, internal feedback on this pin 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 clkout clka4 clka3 v dd gnd clkb4 clkb3 s1 ref clka1 clka2 v dd gnd clkb1 clkb2 s2 soic/tssop top view pin configuration clka1 clka2 clka3 clka4 clkb1 clkb2 clkb3 clkb4 clkout pll mux select input decoding s2 s1 ref block diagram 1 2 3 4 8 7 6 5 clkout clk4 v dd clk3 ref clk2 clk1 gnd soic/tssop top view
mpc962305 low-cost, 3.3v zero delay buffer idt? / ics? 3.3v zero delay buffer 3 mpc962305 rev 7 july 16, 2007 table 3. select input decoding for mpc962309 s2 s1 clock a1?a4 clock b1?b4 clkout (1) 1. this output is driven and has an internal feedback for the pll. the load on this output can be adjusted to change the skew be tween the reference and output. output source pll shutdown 0 0 three-state three-state driven pll n 0 1 driven three-state driven pll n 1 0 driven driven driven reference y 1 1 driven driven driven pll n table 4. maximum ratings characteristics value unit supply voltage to ground potential ? 0.5 to +3.9 v dc input voltage (except ref) ? 0.5 to v dd +0.5 v dc input voltage ref ? 0.5 to 5.5 v storage temperature ? 65 to +150 c junction temperature 150 c static discharge voltage (per mil-std-883, method 3015) >2000 v table 5. operating conditions for mpc962305-x and mpc962309-x industrial temperature devices parameter description min max unit v dd supply voltage 3.0 3.6 v t a operating temperature (ambient temperature) ? 40 85 c c l load capacitance, below 100 mhz 30 pf c l load capacitance, from 100 mhz to 133 mhz 10 pf c in input capacitance 7 pf table 6. electrical characteris tics for mpc962305-x and mpc962309- x industrial temperature devices (1) 1. all parameters are specified with loaded outputs. parameter description test conditions min max unit v il input low voltage (2) 2. ref input has a threshold voltage of v pp /2. 0.8 v v ih input high voltage (2) 2.0 v i il input low current v in = 0 v 50.0 a i ih input high current v in = v dd 100.0 a v ol output low voltage (3) 3. parameter is guaranteed by design and charac terization. not 100% tested in production. i ol = 8 ma ( ? 1) i oh = 12 ma ( ? 1h) 0.4 v v oh output high voltage (3) i oh = ? 8 ma ( ? 1) i ol = ? 12 ma ( ? 1h) 2.4 v i dd (pd mode) power down supply current ref = 0 mhz 25.0 a i dd supply current unloaded outputs at 66.67 mhz, sel inputs at v dd 35.0 ma
mpc962305 low-cost, 3.3v zero delay buffer idt? / ics? 3.3v zero delay buffer 4 mpc962305 rev 7 july 16, 2007 table 7. switching characteristics for mpc962305- 1 and mpc962309-1 industrial temperature devices (1) 1. all parameters are specified with loaded outputs. parameter name test conditions min typ max unit t 1 output frequency 30-pf load 10-pf load 10 10 100 133.33 mhz mhz duty cycle (2) = t 2 t 1 2. parameter is guaranteed by design and char acterization. not 100% tested in production. measured at 1.4 v, f out = 66.67 mhz 40.0 50.0 60.0 % t 3 rise time (2) measured between 0.8 v and 2.0 v 2.50 ns t 4 fall time (2) measured between 0.8 v and 2.0 v 2.50 ns t 5 output to output skew (2) all outputs equally loaded 250 ps t 6a delay, ref rising edge to clkout rising edge (2) measured at v dd /2 0 350 ps t 6b delay, ref rising edge to clkout rising edge (2) measured at v dd /2. measured in pll bypass mode, mpc962309 device only 158.7ns t 7 device to device skew (2) measured at v dd /2 on the clkout pins of devices 0 700 ps t j cycle to cycle jitter (2) measured at 66.67 mhz, loaded outputs 200 ps t lock pll lock time (2) stable power supply, valid cl ock presented on ref pin 1.0 ms table 8. switching characteristics for mpc962305- 1h and mpc962309-1h industrial temperature devices (1) 1. all parameters are spec ified with loaded outputs. parameter name test conditions min typ max unit t 1 output frequency 30-pf load 10-pf load 10 10 100 133.33 mhz mhz duty cycle (2) = t2 t1 2. parameter is guaranteed by design and characterization. not 100% tested in production. measured at 1.4 v, f out = 66.67 mhz 40.0 50.0 60.0 % duty cycle (2) = t2 t1 measured at 1.4 v, f out < 50 mhz 45.0 55.0 55.0 % t 3 rise time (2) measured between 0.8 v and 2.0 v 1.50 ns t 4 fall time (2) measured between 0.8 v and 2.0 v 1.50 ns t 5 output to output skew (2) all outputs equally loaded 250 ps t 6a delay, ref rising edge to clkout rising edge (2) measured at v dd /2 0 350 ps t 6b delay, ref rising edge to clkout rising edge (2) measured at v dd /2. measured in pll bypass mode, mpc962309 device only 158.7ns t 7 device to device skew (2) measured at v dd /2 on the clkout pins of devices 0 700 ps t 8 output slew rate (2) measured between 0.8 v and 2.0 v using test circuit #2 1 v/ns t j cycle to cycle jitter (2) measured at 66.67 mhz, loaded outputs 200 ps t lock pll lock time (2) stable power supply, valid clock presented on ref pin 1.0 ms
mpc962305 low-cost, 3.3v zero delay buffer idt? / ics? 3.3v zero delay buffer 5 mpc962305 rev 7 july 16, 2007 applications information figure 1. output-to-output skew t sk(o) figure 2. static phase offset test reference figure 3. output duty cycle (dc) figure 4. device-to-device skew figure 5. cycle-to-cycle jitter figure 6. output transition time test reference the pin-to-pin skew is defined as t he worst case difference in propagation delay between any similar delay path within a single device v cc 1.4 v gnd v cc 1.4 v gnd t 5 v cc v cc 2 gnd v cc v cc 2 gnd t 6 cclk fb_in the time from the pll controlled edge to the non-controlled edge, divided by the time between pll controlled edges, expressed as a percentage v cc 1.4 v gnd t 2 t 1 dc = t 2 /t 1 x 100% v cc v cc 2 gnd v cc v cc 2 gnd t 7 device 1 device 2 the variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs t n t j = | t n ?t n+1 | t n+1 t 4 t 3 v cc = 3.3 v 2.0 0.8
mpc962305 low-cost, 3.3v zero delay buffer idt? / ics? 3.3v zero delay buffer 6 mpc962305 rev 7 july 16, 2007 table 9. ordering information ordering code package type mpc962305d-1 8-pin 150-mil soic MPC962305D-1R2 8-pin 150-mil soic - tape and reel mpc962305ef-1 8-pin 150-mil soic (pb-free) mpc962305ef-1r2 8-pin 150-mil soic (pb-free) - tape and reel mpc962305d-1h 8-pin 150-mil soic mpc962305d-1hr2 8-pin 150-mil soic - tape and reel mpc962305ef-1h 8-pin 150-mil soic (pb-free) mpc962305ef-1hr2 8-pin 150-mil soic (pb-free) - tape and reel mpc962305dt-1h 8-pin 150-mil tssop mpc962305dt-1hr2 8-pin 150-mil tssop - tape and reel mpc962305ej-1h 8-pin 150-mil tssop (pb-free) mpc962305ej-1hr2 8-pin 150-mil tssop (pb-free) - tape and reel mpc962309d-1 16-pin 150-mil soic mpc962309d-1r2 16-pin 150-mil soic - tape and reel mpc962309ef-1 16-pin 150-mil soic (pb-free) mpc962309ef-1r2 16-pin 150-mil soic (pb-free) - tape and reel mpc962309d-1h 16-pin 150-mil soic mpc962309d-1hr2 16-pin 150-mil soic - tape and reel mpc962309ef-1h 16-pin 150-mil soic (pb-free) mpc962309ef-1hr2 16-pin 150-mil soic (pb-free) - tape and reel mpc962309dt-1h 16-pin 4.4-mm tssop mpc962309dt-1hr2 16-pin 4.4-mm tssop - tape and reel mpc962309ej-1h 16-pin 4.4-mm tssop (pb-free) mpc962309ej-1hr2 16-pin 4.4-mm tssop (pb-free) - tape and reel 0.1 f 0.1 f clk out c load v dd v dd outputs gnd gnd test circuit #1 test circuit for all parameters except t 8 0.1 f 0.1 f clk out 10 pf v dd v dd outputs gnd gnd test circuit #2 test circuit for t 8 , output slew rate on ?1h, ?5 device 1 k ? 1 k ?
mpc962305 low-cost, 3.3v zero delay buffer idt? / ics? 3.3v zero delay buffer 7 mpc962305 rev 7 july 16, 2007 package dimensions case 751-07 issue u 8-lead soic plastic package page 1 of 2
mpc962305 low-cost, 3.3v zero delay buffer idt? / ics? 3.3v zero delay buffer 8 mpc962305 rev 7 july 16, 2007 package dimensions case 751-07 issue u 8-lead soic plastic package page 1 of 3 page 2 of 2
mpc962305 low-cost, 3.3v zero delay buffer idt? / ics? 3.3v zero delay buffer 9 mpc962305 rev 7 july 16, 2007 package dimensions case 751b-05 issue l 16-lead soic plastic package page 1 of 2
mpc962305 low-cost, 3.3v zero delay buffer idt? / ics? 3.3v zero delay buffer 10 mpc962305 rev 7 july 16, 2007 package dimensions case 751b-05 issue l 16-lead soic plastic package page 2 of 2
mpc962305 low-cost, 3.3v zero delay buffer idt? / ics? 3.3v zero delay buffer 11 mpc962305 rev 7 july 16, 2007 package dimensions case 948f-01 issue b 16-lead tssop plastic package page 1 of 3
mpc962305 low-cost, 3.3v zero delay buffer idt? / ics? 3.3v zero delay buffer 12 mpc962305 rev 7 july 16, 2007 package dimensions case 948f-01 issue b 16-lead tssop plastic package page 2 of 3
mpc962305 low-cost, 3.3v zero delay buffer idt? / ics? 3.3v zero delay buffer 13 mpc962305 rev 7 july 16, 2007 package dimensions case 948f-01 issue b 16-lead tssop plastic package page 3 of 3
mpc962305 low-cost, 3.3v zero delay buffer idt? / ics? 3.3v zero delay buffer 14 mpc962305 rev 7 july 16, 2007 package dimensions case 948j-01 issue b 8-lead tssop plastic package page 1 of 3
mpc962305 low-cost, 3.3v zero delay buffer idt? / ics? 3.3v zero delay buffer 15 mpc962305 rev 7 july 16, 2007 package dimensions case 948j-01 issue b 8-lead tssop plastic package page 2 of 3
mpc962305 low-cost, 3.3v zero delay buffer idt? / ics? 3.3v zero delay buffer 16 mpc962305 rev 7 july 16, 2007 package dimensions case 948j-01 issue b 8-lead tssop plastic package page 3 of 3
mpc962305 low-cost, 3.3v zero delay buffer ? 2007 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 innovate with idt and accelerate your future netw orks. contact: www.idt.com

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